test sequence class

OPPRU 2025. 2. 23. 11:14

※ pipe_basic_vseq.sv

// Base sequence
class pipe_base_seq_c extends uvm_sequence;
  `uvm_object_utils_begin(pipe_base_seq_c)
  `uvm_object_utils_end

  `uvm_declare_p_sequencer(vseqr_c)

  function new (string name = "pipe_base_seq_c");
    super.new(name);
  endfunction

  virtual task pre_body();
    super.pre_body();

    if (starting_phase != null) begin
      `uvm_info(get_type_name(), $sformatf("Raise objection"), UVM_LOW)
      starting_phase.raise_objection(this, get_type_name()); // raise an objection
    end
  endtask

  virtual task body();
    //super.body(); // warning) Body definitition undefined.
    //..
  endtask

  virtual task post_body();
    super.post_body();

    if (starting_phase != null) begin
      `uvm_info(get_type_name(), $sformatf("Drop objection"), UVM_LOW)
      starting_phase.drop_objection(this, get_type_name()); // drop an objection
    end
  endtask
endclass


// Test sequence(virtual sequence)
class pipe_basic_vseq_c extends pipe_base_seq_c;
  `uvm_object_utils(pipe_basic_vseq_c)

  pipe_drv_pkt_c pkt;

  function new (string name = "pipe_basic_vseq_c");
    super.new(name);
  endfunction

  virtual task pre_body();
    super.pre_body();
    `uvm_info(get_type_name(), $sformatf("pre_body() starts.."), UVM_LOW)
  endtask

  virtual task body();
    super.body();
    `uvm_info(get_type_name(), $sformatf("Start Test"), UVM_LOW)

    wait_for_reset_release();

    `uvm_create_on(pkt, p_sequencer.pipe_seqr)
    repeat(20) begin
assert(pkt.randomize() with {
i_enable == 1'b1;
});
`uvm_info(get_type_name(), $sformatf("[%2d]Send Packets", $time), UVM_LOW)
`uvm_send(pkt);
    end

    assert(pkt.randomize() with {
      i_cf == 2'b0;
      i_enable == 1'b0;
      i_data_in0 == 16'h0;
      i_data_in1 == 16'h0;
    });
    `uvm_info(get_type_name(), $sformatf("[%2d]Send Packets", $time), UVM_LOW)
    `uvm_send(pkt);

    repeat(10) @(posedge p_sequencer.vif.CLK);
    `uvm_info(get_type_name(), $sformatf("Finish Test"), UVM_LOW)
  endtask


  virtual task post_body();
    super.post_body();
    `uvm_info(get_type_name(), $sformatf("post_body() starts.."), UVM_LOW)
  endtask

  virtual task wait_for_reset_release();
    @(posedge p_sequencer.vif.RSTN);
    `uvm_info(get_type_name(), $sformatf("System reset is released."), UVM_LOW)
    repeat(10) @(posedge p_sequencer.vif.CLK);
    `uvm_info(get_type_name(), $sformatf("Wait for 10 clock cycles."), UVM_LOW)
  endtask

endclass