OPPRU LAB

  • -
    • 소개
    • [1] RTL Design
    • [2] SystemVerilog
    • [3] Design Verification
    • [4] UVM
    • [5] DV Practice
      • [EDA Link 주소]
      • DuT & Specifications
      • TB Architecture
      • TB Setup
      • └ ⑴ tb_top module
      • └ ⑵ test class
      • └ ⑶ tb class
      • └ ⑷ env class
      • └ ⑸ virtual sequencer class
      • └ ⑹ transaction class
      • └ ⑺ agent class
      • └ ⑻ sequencer, driver, mon..
      • └ ⑼ scoreboard class
      • └ ⑽ uvm package
      • └ ⑾ test sequence class
      • Test Simulation
  • 방명록
/ /

전체 글

  • uvm package 2025.03.03
  • scoreboard class 2025.03.03
  • sequencer, driver, monitor class 2025.03.03
  • agent class 2025.02.23
  • transaction class 2025.02.23
  • virtual sequencer class 2025.02.23
  • env class 2025.02.23
  • tb class 2025.02.23
  • test sequence class 2025.02.23
  • test class 2025.02.23
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