※ pipe_sequencer.sv |
class pipe_sequencer_c extends uvm_sequencer#(pipe_drv_pkt_c); `uvm_component_utils(pipe_sequencer_c) function new(string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); `uvm_info(get_type_name(), $sformatf("build_phase() starts.."), UVM_LOW) endfunction endclass |
※ pipe_driver.sv |
class pipe_driver_c extends uvm_driver#(pipe_drv_pkt_c); `uvm_component_utils(pipe_driver_c) virtual interface pipe_if vif; function new(string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); `uvm_info(get_type_name(), $sformatf("build_phase() starts.."), UVM_LOW) //Get interface from uvm_config_db if (!uvm_config_db#(virtual pipe_if)::get(this, "", "vif", vif)) begin `uvm_fatal(get_type_name(), {"virtual interface must be set for: ", get_full_name(), ".vif"}) end endfunction virtual task run_phase(uvm_phase phase); super.run_phase(phase); `uvm_info(get_type_name(), $sformatf("run_phase() starts.."), UVM_LOW) reset_signals(); forever begin drive_signals(); end endtask virtual task reset_signals(); @(negedge vif.RSTN); vif.I_CF = 'h0; vif.I_ENABLE = 'h0; vif.I_DATA_IN0 = 'h0; vif.I_DATA_IN1 = 'h0; endtask virtual task drive_signals(); `uvm_info(get_type_name(), $sformatf("drive interface signals."), UVM_LOW) seq_item_port.get_next_item(req); @(posedge vif.CLK); vif.I_CF = req.i_cf; vif.I_ENABLE = req.i_enable; vif.I_DATA_IN0 = req.i_data_in0; vif.I_DATA_IN1 = req.i_data_in1; seq_item_port.item_done(); endtask endclass |
※ pipe_monitor.sv |
class pipe_monitor_c extends uvm_monitor; `uvm_component_utils(pipe_monitor_c) uvm_analysis_port #(pipe_mon_pkt_c) data_port; // TLM port broadcast mode virtual interface pipe_if vif; pipe_mon_pkt_c pkt; function new(string name, uvm_component parent); super.new(name, parent); data_port = new("data_port", this); endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); `uvm_info(get_type_name(), $sformatf("build_phase() starts.."), UVM_LOW) if (!uvm_config_db#(virtual pipe_if)::get(this, "", "vif", vif)) begin `uvm_fatal(get_type_name(), {"virtual interface must be set for: ", get_full_name(), ".vif"}) end endfunction virtual task run_phase(uvm_phase phase); super.run_phase(phase); pkt = pipe_mon_pkt_c::type_id::create("pkt"); forever begin @(posedge vif.CLK); pkt.i_cf = vif.I_CF; pkt.i_enable = vif.I_ENABLE; pkt.o_enable = vif.O_ENABLE; if (vif.I_ENABLE) begin pkt.i_data_in0 = vif.I_DATA_IN0; pkt.i_data_in1 = vif.I_DATA_IN1; end if (vif.O_ENABLE) begin `uvm_info(get_type_name(), $sformatf("get interface output signals."), UVM_LOW) pkt.o_data_in0 = vif.O_DATA_OUT0; pkt.o_data_in1 = vif.O_DATA_OUT1; //`uvm_info(get_type_name(), $sformatf("pkt.o_data_in0 = 'h%x", pkt.o_data_in0), UVM_LOW) //`uvm_info(get_type_name(), $sformatf("pkt.o_data_in1 = 'h%x", pkt.o_data_in1), UVM_LOW) end data_port.write(pkt); // transaction calling by TLM port end endtask endclass |